UppLYSning Lysator Seminar Series

23/10: The Race to Petaflops: Getting it Right

With Thomas Sterling (CACR, Caltech and High Performance Computing Systems Group, Jet Propulsion Laboratory)

Time: 18.15 - 20.00. Location: C4.

The steady increase in performance of high end computing systems as reflected by the Top-500 list demonstrates an average performance gain of a factor of approximately 1.8X per year as measured by the Linpack benchmark over a baseline of almost a decade.

This apparent sustained rate of growth obscures the highly non-linear trends in the underlying system architectures. When nine years ago vector, SIMD, and SMP architectures dominated much of the HPC landscape, today almost all of the top performing systems are MPPs and commodity clusters (including Constellations) with the Japanese Earth Simulator the fastest general purpose system at 40 Teraflops peak comprising an MPP of vector microprocessors establishing the mid point (logarithmically) in the trans-Teraflops performance regime.

The implications of these trends is that Petaflops scale computing systems will become available at the beginning of the next decade but that the class of system architecture may have to be very different from the MPP and clusters systems of today.

This presentation describes some of the possible alternative system architectures that may drive computing in to the trans-Petaflops regime. In particular, hybrid technology and processor in memory (PIM) architectures will be examined in their various forms. Of equal importance is how such systems will address critical factors that contribute to performance degradation and inefficiency including latency, overhead, starvation, and contention. The talk will conclude with a brief discussion on the new Cray Cascade Petaflops computer project being sponsored by DARPA.

This talk is presented in cooperation with NSC:s 3rd Annual Workshop on Linux Clusters for Super Computing. Please visit their web page if you want to attend the workshop.

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